In the fabrication of integrated circuit devices, the trend has generally been toward reducing packaging size. As a result, various high density interconnection ("HDI") techniques have been developed. One such conventional fabrication process is to place integrated circuit chips, or dies, in cavities formed in a substrate base so that the top surfaces of the chips are essentially planar with the surface of the substrate. The cavities are generally formed in the substrate utilizing a conventional milling process. After the chips are placed in the cavities, a film sheet of dielectric laminate is layered over the chips and the dielectric layer is then etched with a pattern of metallization to selectively interconnect the chips. Such a process requires precise tolerances in the milling of the cavities, and problems may arise if the chips are of varying or non-uniform thickness.
Another conventional fabrication process utilizes a flip chip attachment for affixing an integrated circuit chip to the substrate. In the flip chip method, the integrated circuit chip is patterned with various connection points which are to make contact with selected points on an integrated circuit formed on a substrate. The integrated circuit chip must then be placed precisely in a select location on the integrated circuit formed on the substrate. The flip chip attachment requires additional silicon processing steps and makes testing of components very difficult, which in turn limits the number of vendors and availability of chips used for this application. Further, the flip chip attachment may encounter problems when encapsulating the chip with a CTE mismatched material to silicon.
Still another conventional fabrication process involves attaching the integrated circuit chip to an integrated circuit formed on a substrate with a non-conductive adhesive and physically wirebonding the integrated circuit chip to select points on the integrated circuit formed on the substrate. The wirebonding method includes physically attaching the various connection wires projecting from the integrated circuit chip to various points on the integrated circuit formed on the substrate. Since integrated circuits generally place components as close as possible in order to minimize size, such physical attachment may prove difficult, cumbersome, and increase the bulkiness of the integrated circuit device.
The present invention is directed toward overcoming one or more of the above-mentioned problems.